Job id : 42909
ASIC Design Engineer
ASIC Design Engineer
Pune
2 years ago
JOB ID:42909
Job details
Job Type
Full Time
Functional Area
Software Development
Industry
Electrical/Electronics/Semiconductor
Education
Not Specified
Experience Required
8 - 15 Yrs
Key Skills Required
uvm, c/c++, asic design, verilog and systemverilog., perl/python
Other Skills Required
Job Description
ASIC Design Engineer
The OpportunityMarvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Design Engineer role, you will be responsible for developing and architecting RTL and taking it to silicon using the latest techniques, such as emulation and formal verification. You will part of a team that takes a product from concept to completion and from prototype to mass production. You will be involved in pre-silicon design development all the way to real data center problem debug and resolution.o 8+ years of ASIC design experience using Verilog and SystemVerilog.
o The ability to read block level specifications and implement in RTL.
o Work independently to develop block and cluster level design solutions.
o Ability to create self-checking and reusable test benches. The ability to do some level of verification of design blocks is required
o Ability to work closely with analog designers when interfacing to and integrating ... See More
The OpportunityMarvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Design Engineer role, you will be responsible for developing and architecting RTL and taking it to silicon using the latest techniques, such as emulation and formal verification. You will part of a team that takes a product from concept to completion and from prototype to mass production. You will be involved in pre-silicon design development all the way to real data center problem debug and resolution.o 8+ years of ASIC design experience using Verilog and SystemVerilog.
o The ability to read block level specifications and implement in RTL.
o Work independently to develop block and cluster level design solutions.
o Ability to create self-checking and reusable test benches. The ability to do some level of verification of design blocks is required
o Ability to work closely with analog designers when interfacing to and integrating ... See More
ASIC Design Engineer
The OpportunityMarvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Design Engineer role, you will be responsible for developing and architecting RTL and taking it to silicon using the latest techniques, such as emulation and formal verification. You will part of a team that takes a product from concept to completion and from prototype to mass production. You will be involved in pre-silicon design development all the way to real data center problem debug and resolution.o 8+ years of ASIC design experience using Verilog and SystemVerilog.
o The ability to read block level specifications and implement in RTL.
o Work independently to develop block and cluster level design solutions.
o Ability to create self-checking and reusable test benches. The ability to do some level of verification of design blocks is required
o Ability to work closely with analog designers when interfacing to and integrating analog IP is an advantage.
o Ability to assist in post silicon validation efforts and debug.
o Knowledge in Formal is an advantage.
o Knowledge of synthesis and netlist simulation is an advantage
o Knowledge of scripting languages (Perl/Python)
o Knowledge in C/C++ is an advantage
o Knowledge of UVM is an advantage See Less
The OpportunityMarvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Design Engineer role, you will be responsible for developing and architecting RTL and taking it to silicon using the latest techniques, such as emulation and formal verification. You will part of a team that takes a product from concept to completion and from prototype to mass production. You will be involved in pre-silicon design development all the way to real data center problem debug and resolution.o 8+ years of ASIC design experience using Verilog and SystemVerilog.
o The ability to read block level specifications and implement in RTL.
o Work independently to develop block and cluster level design solutions.
o Ability to create self-checking and reusable test benches. The ability to do some level of verification of design blocks is required
o Ability to work closely with analog designers when interfacing to and integrating analog IP is an advantage.
o Ability to assist in post silicon validation efforts and debug.
o Knowledge in Formal is an advantage.
o Knowledge of synthesis and netlist simulation is an advantage
o Knowledge of scripting languages (Perl/Python)
o Knowledge in C/C++ is an advantage
o Knowledge of UVM is an advantage See Less
About Company
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you.
Our leading-edge solutions are the essential building blocks of the infrastructure technology of the future. And that success is dependent on the tenacity of our global team coming together to lead that change. At Marvell, everyone has an important role to play in changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
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