Job id : 42893
Physical Design Senior Engineer
Physical Design Senior Engineer
Bangalore
2 years ago
11 Applied
JOB ID:42893
Job details
Job Type
Freelance
Functional Area
RnD/Engineering design,Engineering - Electrical
Industry
Electrical/Electronics/Semiconductor
Education
Not Specified
Experience Required
8 - 12 Yrs
Key Skills Required
design compiler/rtl compiler, innovus/icc2, primetime/tempus, qrc/starxt, calibr, rtl2gdsii implementation, physical design/sta
Other Skills Required
Job Description
Physical Design Senior Engineer
The Opportunity
Roles and Responsibilitieso The roles and responsibilities of engineer require in-depth knowledge and hands-on experience across the entire spectrum of RTL2GDSII Implementation i.e. Synthesis, Floorplanning, Power Grid Design, Placement, Clock implementation, Routing, STA, Electrical signoff, Power-Analysis, Physical Verification, Chip finishing, etc.
o Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goal
o Interact with the design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas
o Debug design, timing constraint issues and feedback to design team
o Analyze results from signoff checks and achieve design closureRequired Skillso 8+ years of experience in Physical Design/STA role
o End-to-end physical implementation experience on multi-million gate-count design
o Ability to plan and work independently and coordinate with cross-functional teams
o ... See More
The Opportunity
Roles and Responsibilitieso The roles and responsibilities of engineer require in-depth knowledge and hands-on experience across the entire spectrum of RTL2GDSII Implementation i.e. Synthesis, Floorplanning, Power Grid Design, Placement, Clock implementation, Routing, STA, Electrical signoff, Power-Analysis, Physical Verification, Chip finishing, etc.
o Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goal
o Interact with the design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas
o Debug design, timing constraint issues and feedback to design team
o Analyze results from signoff checks and achieve design closureRequired Skillso 8+ years of experience in Physical Design/STA role
o End-to-end physical implementation experience on multi-million gate-count design
o Ability to plan and work independently and coordinate with cross-functional teams
o ... See More
Physical Design Senior Engineer
The Opportunity
Roles and Responsibilitieso The roles and responsibilities of engineer require in-depth knowledge and hands-on experience across the entire spectrum of RTL2GDSII Implementation i.e. Synthesis, Floorplanning, Power Grid Design, Placement, Clock implementation, Routing, STA, Electrical signoff, Power-Analysis, Physical Verification, Chip finishing, etc.
o Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goal
o Interact with the design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas
o Debug design, timing constraint issues and feedback to design team
o Analyze results from signoff checks and achieve design closureRequired Skillso 8+ years of experience in Physical Design/STA role
o End-to-end physical implementation experience on multi-million gate-count design
o Ability to plan and work independently and coordinate with cross-functional teams
o Good knowledge of low power concepts and application to PD
o Experience in formal verification for RTL 2 gates and gates2gates, low power verification is a must
o Exposure to low-power designs with CPF/UPF flow
o Knowledge of CTS, Clock tree methodology and clock skewing
o Power grid, clock tree, and low-power reduction implementation methods
o Excellent STA tool and timing concept understanding for analysis & debug of problems and closure methodologies
o Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing/MMMC and multi-power designs (Level shifters, Isolation cells etc.)
o Must have experience in ECO implementation
o Understanding of Physical Verification Flows is an advantage
o Programming and scripting skills (Tcl, Perl, etc.)
o Experience with cutting edge technology node designs like 16nm, 12nm, 7nm
o Experience of networking design would be a plus
o Hands-on expertise with industry-standard EDA tools including but not limited to Design Compiler/RTL Compiler, Innovus/ICC2, Primetime/Tempus, QRC/StarXT, Calibr See Less
The Opportunity
Roles and Responsibilitieso The roles and responsibilities of engineer require in-depth knowledge and hands-on experience across the entire spectrum of RTL2GDSII Implementation i.e. Synthesis, Floorplanning, Power Grid Design, Placement, Clock implementation, Routing, STA, Electrical signoff, Power-Analysis, Physical Verification, Chip finishing, etc.
o Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goal
o Interact with the design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas
o Debug design, timing constraint issues and feedback to design team
o Analyze results from signoff checks and achieve design closureRequired Skillso 8+ years of experience in Physical Design/STA role
o End-to-end physical implementation experience on multi-million gate-count design
o Ability to plan and work independently and coordinate with cross-functional teams
o Good knowledge of low power concepts and application to PD
o Experience in formal verification for RTL 2 gates and gates2gates, low power verification is a must
o Exposure to low-power designs with CPF/UPF flow
o Knowledge of CTS, Clock tree methodology and clock skewing
o Power grid, clock tree, and low-power reduction implementation methods
o Excellent STA tool and timing concept understanding for analysis & debug of problems and closure methodologies
o Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing/MMMC and multi-power designs (Level shifters, Isolation cells etc.)
o Must have experience in ECO implementation
o Understanding of Physical Verification Flows is an advantage
o Programming and scripting skills (Tcl, Perl, etc.)
o Experience with cutting edge technology node designs like 16nm, 12nm, 7nm
o Experience of networking design would be a plus
o Hands-on expertise with industry-standard EDA tools including but not limited to Design Compiler/RTL Compiler, Innovus/ICC2, Primetime/Tempus, QRC/StarXT, Calibr See Less
About Company
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you.
Our leading-edge solutions are the essential building blocks of the infrastructure technology of the future. And that success is dependent on the tenacity of our global team coming together to lead that change. At Marvell, everyone has an important role to play in changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
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