Job id : 41443
DFT engineer
DFT engineer
Pune
2 years ago
18 Applied
JOB ID:41443
Job details
Job Type
Full Time
Functional Area
Other
Industry
Electrical/Electronics/Semiconductor
Education
B.Tech/B.E-Electronics/Telecommunication
Experience Required
9 - 18 Yrs
Key Skills Required
ATPG, MBIST, BIST, scan compression, RTL, DFT, ATE, ASIC
Other Skills Required
Languages
English
Job Description
Senior level DFT Engineer - ASICWe are currently on the search for a super star to implement modern DFT solutions for leading edge ICs on latest technology nodes. In this role, you will:
- Work with RTL, custom digital/analog, verification and physical implementation teams during DFT implementation.
- Work with cross functional groups to verify DFT implementation pre tape-out
- Drive successful bring-up of test features post tape-out.
- Add to the in-house expertise on DFT to consult with, educate, and train design staffmembers on DFT requirements on how to prepare new designs to work properly with Cavium DFT solutions.
- Hands-on experience with scan test, logic and memory BIST/BISR, functional test, JTAG, and other test methodologies
- Strong background in industry standard scan test (including scan compression) andmemory BIST/BISR tools
- Strong background in IC RTL design and using Verilog/SystemVerilog
- Experience and knowledge of Synthesis, IC routing and static timing tools
- Experience and k
Senior level DFT Engineer - ASICWe are currently on the search for a super star to implement modern DFT solutions for leading edge ICs on latest technology nodes. In this role, you will:
- Work with RTL, custom digital/analog, verification and physical implementation teams during DFT implementation.
- Work with cross functional groups to verify DFT implementation pre tape-out
- Drive successful bring-up of test features post tape-out.
- Add to the in-house expertise on DFT to consult with, educate, and train design staffmembers on DFT requirements on how to prepare new designs to work properly with Cavium DFT solutions.
- Hands-on experience with scan test, logic and memory BIST/BISR, functional test, JTAG, and other test methodologies
- Strong background in industry standard scan test (including scan compression) andmemory BIST/BISR tools
- Strong background in IC RTL design and using Verilog/SystemVerilog
- Experience and knowledge of Synthesis, IC routing and static timing tools
- Experience and knowledge of functional verification, especially of DFT features
- Experience and knowledge of modern JTAG standards and implementation
- Experience and knowledge of high-volume test equipment (ATE) and system-level test (SLT)
- Proficiency with programming and scripting languages such as Perl/TCL
- Experience with board/bench debug features and capabilities strongly desired
- Must have effective interpersonal and teamwork skills.
- Proficiency in working with cross functional and cross site teams.
- Excellent communication skills
- Demonstrates good analysis and problem-solving skills.
- Has an inherent sense of urgency and accountability.
- Must have the ability to multi-task in a fast paced environment
- MSEE or equivalent with 9+ years of experience in design for test
Additional Information
Cab Facility Provided
Flexibility ProvidedAbout Company
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you.
Our leading-edge solutions are the essential building blocks of the infrastructure technology of the future. And that success is dependent on the tenacity of our global team coming together to lead that change. At Marvell, everyone has an important role to play in changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
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