Job id : 42910
Design Verification
Design Verification
Pune
2 years ago
JOB ID:42910
Job details
Job Type
Full Time
Functional Area
Software Development
Industry
Electrical/Electronics/Semiconductor
Education
Not Specified
Experience Required
5 - 10 Yrs
Key Skills Required
uvm, asic design, verilog and systemverilog., tcl scripting, jasper
Other Skills Required
Job Description
Design Verification
The Opportunity
Marvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Verification Engineer role, you will be responsible for developing verification plans and
architecting test benches to validate DUT (Devise Under Test) functionality in simulation using the latest techniques such as
UVM, Formal Verification, System Verilog and Emulation.Responsibilities
Marvell is looking for highly skilled verification engineers with the following knowledge:
o Experience: 5+ years
o System Verilog UVM methodology
o Have design a block level environment from scratch
o Block level to cluster level integration knowledge
o Random environment with functional coverage-based verification
o Formal knowledge is an advantage
o Write test plan
o Fast learner
o PCIe protocol knowledge
o Ethernet knowledgeRequirements
Formal Verification engineers with the following knowledge:
o Jasper
o Good knowledge of formal methodologies
o Done form... See More
The Opportunity
Marvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Verification Engineer role, you will be responsible for developing verification plans and
architecting test benches to validate DUT (Devise Under Test) functionality in simulation using the latest techniques such as
UVM, Formal Verification, System Verilog and Emulation.Responsibilities
Marvell is looking for highly skilled verification engineers with the following knowledge:
o Experience: 5+ years
o System Verilog UVM methodology
o Have design a block level environment from scratch
o Block level to cluster level integration knowledge
o Random environment with functional coverage-based verification
o Formal knowledge is an advantage
o Write test plan
o Fast learner
o PCIe protocol knowledge
o Ethernet knowledgeRequirements
Formal Verification engineers with the following knowledge:
o Jasper
o Good knowledge of formal methodologies
o Done form... See More
Design Verification
The Opportunity
Marvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Verification Engineer role, you will be responsible for developing verification plans and
architecting test benches to validate DUT (Devise Under Test) functionality in simulation using the latest techniques such as
UVM, Formal Verification, System Verilog and Emulation.Responsibilities
Marvell is looking for highly skilled verification engineers with the following knowledge:
o Experience: 5+ years
o System Verilog UVM methodology
o Have design a block level environment from scratch
o Block level to cluster level integration knowledge
o Random environment with functional coverage-based verification
o Formal knowledge is an advantage
o Write test plan
o Fast learner
o PCIe protocol knowledge
o Ethernet knowledgeRequirements
Formal Verification engineers with the following knowledge:
o Jasper
o Good knowledge of formal methodologies
o Done formal block level verification
o TCL scripting
o Write test plan
o Build formal methodologies See Less
The Opportunity
Marvell’s Ethernet and Fibre Channel ASIC group innovates cutting edge data center hardware.
As a part of this group in an ASIC Verification Engineer role, you will be responsible for developing verification plans and
architecting test benches to validate DUT (Devise Under Test) functionality in simulation using the latest techniques such as
UVM, Formal Verification, System Verilog and Emulation.Responsibilities
Marvell is looking for highly skilled verification engineers with the following knowledge:
o Experience: 5+ years
o System Verilog UVM methodology
o Have design a block level environment from scratch
o Block level to cluster level integration knowledge
o Random environment with functional coverage-based verification
o Formal knowledge is an advantage
o Write test plan
o Fast learner
o PCIe protocol knowledge
o Ethernet knowledgeRequirements
Formal Verification engineers with the following knowledge:
o Jasper
o Good knowledge of formal methodologies
o Done formal block level verification
o TCL scripting
o Write test plan
o Build formal methodologies See Less
About Company
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you.
Our leading-edge solutions are the essential building blocks of the infrastructure technology of the future. And that success is dependent on the tenacity of our global team coming together to lead that change. At Marvell, everyone has an important role to play in changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
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